hc24.hotchips.orgHot Chips: A Symposium on High Performance Chips | Conference Sponsor IEEE Technical Committee on

Microprocessors and Microcomputers. Hot Chips: A Symposium on High Performance Chips Conference Sponsor IEEE Technical Committee on Microprocessors and Microcomputers. Search About HC24 (2012) August 27-29, 2012 at Flint Center, Cupertino, CA Combined PDF’s Tutorials Conference Tutorials, August 27, 2012 Tutorial 1: (The Evolution of) Mobile SoC Programming, Neil Trevett (Host), Khronos Mobile devices are driving a revolution in how computing is accessible by all. Users can now carry devices in their pockets that grant unfettered access to and facile manipulation of their data, redefining how people work and relate to each other. The blunt instrument of Moore’s law performance scaling has certainly contributed to this trend. However, the demands of graceful industrial design (thermals, PCB area), friction-free user interfaces (smooth performance), and long-term wire-free usage (battery life and unconstrained wireless connectivity) has forced architects of System-on-Chip” (SoC) designs to take more nuanced approaches to utilizing increasing transistor density. This includes the integration of many purpose optimized logic blocks, programmable and non-programmable, which, when properly orchestrated with other (traditional) SoC components like CPUs and GPUs, deliver low-power implementations of common use-cases for these devices. The challenge for Operating System vendors and developers is how to enable this orchestration efficiently for the burgeoning market of mobile and tablet-optimized applications (which is nearing millions of applications across all platforms). For optimal power at best quality, it is not unusual for the app developer to either implicitly or explicitly program upwards of a dozen pieces of chip IP, each with it’s own programming model and performance/power characteristics. How are the OS vendors enabling this vibrant and growing applications ecosystem in the presence of such daunting programming problems? This tutorial will review the current landscape of mobile SoCs and their future direction (a hint: we’re integrating more functionality than ever on a single die). We will describe how the complexity of developing for these SoCs is tamed by today’s APIs and what challenges remain. We will also discuss how future use-cases will demand additional capabilities be enabled, impacting everything from chip design to OS to high-level APIs. Khronos Connects Software to Silicon , Neil Trevett, Khronos ArcSoft Multi-Frame Technologies , Sean Mao, ArcSoft Touch-free Technology , Itay Katz, eyeSight Augmented Reality , Ben Blachnitzky, Metaio Sensor Fusion: Mobile Platform Challenges and Future Directions Jim Steele, Sensor Platforms Platform Performance , Daniel Wexler, the 11ers Tutorial 2: Die Stacking 2.5D/3D die stacking increases aggregate inter-chip bandwidth and shrinks board footprint while reducing I/O latency and energy consumption. By integrating in one package multiple tightly-coupled semiconductor dice – each possibly in a process optimized for power, performance and costs for a particular function – this technology gives system designers additional options to partition and scale solutions efficiently. Die stacking has already transformed the design of high-end CMOS image sensors, and it promises to also enhance FPGA, graphics and mobile applications. In Part 1 of this tutorial we will examine the key enabling technologies such as silicon interposer, TSV, micro-bump and assembly integration. In Part 2 we will cover the design considerations & trade-offs of 2.5D/3D in CAD, ESD and architecture. Part 3 will showcase how the technology is used in systems and applications for memory integration, optics integration and monolithic die partitioning. Introduction , Liam Madden, Xilinx Foundry TSV Enablement For 2.5D/3D Chip Stacking , Remi Yu, UMC Full Processing Interposer Process , Choon Lee, Amkor Roadmap for Design and EDA Infrastructure for 3D Products , Riko Radojcic, Qualcomm Xilinx SSI Technology: Concept to Silicon Development Overview , Shankar Lakka, Xilinx Die Stacking and the System , Bryan Black, AMD Optical Backplanes with 3D Integrated Photonics? Ephrem Wu, Xilinx Conference Day 1, August 28, 2012 Introductory Remarks , Christos Kozyrakis and Rumi Zahir Session 1: Microprocessors Architecture and power management of the Third generation Intel Core micro architecture , Sanjeev Jahagirdar, Intel AMD’s Jaguar”: A next generation low power x86 core. , Jeff Rupley, AMD proAptiv: Efficient Performance on a Fully-Synthesizable Core , Ranganathan Sudhakar, MIPS Session 2: Fabrics and Interconnects Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems , Ronald Dreslinski, University of Michigan FPGA Augmented ASICs: The Time Has Come , David Riddoch, Solarflare SwitchX Architecture , Diego Crupnicoff, Mellanox Keynote 1: The Surround Computing Era The Surround Computing Era , Mark Papermaster, CTO of AMD Session 3: Many Core and GPU AMD HD7970 Graphics Core Next (GCN) Architecture , Michael Mantor, AMD AMD Trinity Fusion APU , Sebstian Nussbaum, AMD Knights Corner, Intel’s first Many Integrated Core (MIC) Architecture Product , George Chrysos, Intel Session 4: Multimedia and Imaging ADI’s Revolutionary BF60x Vision Focused Digital Signal Processor System On Chip : 25 Billion Operations/Sec @ 80 mW and Zero Bandwidth , Robert Bushey, ADI Visconti2 – A Heterogeneous Multi-Core SoC for Image-Recognition Applications , Masato Uchiyama, Toshiba Session 5: Integration Centip3De: A 64-Core, 3D Stacked, Near-Threshold System , Ronald Dreslinski, University of Michigan FPGAs with 28Gbps Transceivers Built with Heterogeneous Stacked-Silicon Interconnects , Ephrem Wu, Xilinx Keynote 2: The Future of Wireless Networking The Future of Wireless Networking , Marcus Weldon, CTO of Alcatel-Lucent Conference Day 2, August 29, 2012 Session 6: Technology and Scalability Floating-Point Matrix Processing using FPGAs , Michael Parker, Altera An IA-32 Processor with a Wide Voltage Operating Range in 32nm CMOS , Gregory Ruhl, Intel Reducing Transistor Variability For High Performance Low Power Chips , Robert Rogenmoser, SuVolta Session 7: SoC High performance and efficient single-chip small cell base station SoC , Kin-Yip Liu, Cavium FSM™ (Femtocell Station Modem) – A highly integrated, performance driven, chipset solution for the small cell market , Luca Blessent, Qualcomm Medfield Smartphone – Intel’s ATOM Z2460 Processor , Rumi Zahir, Intel Keynote 3: Cloud Transforms IT, Big Data Transforms Business Cloud Transforms IT, Big Data Transforms Business , Pat Gelsinger, COO Infrastructure Products, EMC Session 8: Data Center Chips POWER7+™: IBM’s Next Generation POWER Microprocessor , Scott Taylor, IBM Xeon E5 2600: Power/Performance Efficiency in the Data Center , Mark Rowland, Intel X-Gene: AppliedMicro’s 64bit ARM CPU and SOC , Gaurav Singh, AMCC Session 9: Big Iron SPARC64 X; Fujitsu’s new generation 16 core processor for the next generation UNIX servers , Takumi Maruyama, Fujitsu 16-core SPARC T5 CMT Processor with glueless 1-hop scaling to 8-sockets , Sebastian Turullols and Ram Sivaramakrishnan, Oracle IBM zNext: the 3rd Generation High Frequency Microprocessor Chip , Kevin Shum, IBM Posters High Performance State Retention with Power Gating applied to CPU subsystems – design approaches and silicon evaluation , David Flynn, Fellow, R&D ARM Ltd, Cambridge, UK Prototyping the DySER Specialization Architecture with OpenSPARC , Jesse Benson, Ryan Cofell, Chris Frericks, Venkatraman Govindaraju, Chen-Han Ho, Zachary Marzec, Tony Nowatzki, Karu Sankaralingam University of Wisconsin-Madison Low Power and High Performance 3‐D Multimedia Platform , Po‐Han Huang, Chi‐Hung Lin, Hsien‐Ching Hsieh, Huang‐Lun Lin and Shing‐Wu Tung Information and Communications Research Lab. Industrial Technology Research Institute The Model Is Not Enough: Understanding Energy Consumption in Mobile Devices , James Bornholt, Australian National University,...